Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating

ABSTRACT

The present invention generally provides a process for depositing silicon carbide using a silane-based material with certain process parameters that is useful for forming a suitable ARC for IC applications. The same material may also be used as a barrier layer and an etch stop, even in complex damascene structures and with high diffusion conductors such as copper as a conductive material. Under certain process parameters, a fixed thickness of the silicon carbide may be used on a variety of thicknesses of underlying layers. The thickness of the silicon carbide ARC is substantially independent of the thickness of the underlying layer for a given reflectivity, in contrast to the typical need for adjustments in the ARC thickness for each underlying layer thickness to obtain a given reflectivity. A preferred process sequence for forming a silicon carbide anti-reflective coating on a substrate, comprises introducing silicon, carbon, and a noble gas into a reaction zone of a process chamber, initiating a plasma in the reaction zone, reacting the silicon and the carbon in the presence of the plasma to form silicon carbide, and depositing a silicon carbide anti-reflective coating on a substrate in the chamber. Another aspect of the invention includes a substrate having a silicon carbide anti-reflective coating, comprising a dielectric layer deposited on the substrate and a silicon carbide anti-reflective coating having a dielectric constant of less than about 7.0 and preferably about 6.0 or less.

[0001] This application is a continuation-in-part of U.S. Ser. No.09/165,248, entitled “A Silicon Carbide Deposition For Use As A BarrierLayer And An Etch Stop, filed Oct. 1, 1998, and claims priority thereto.

FIELD OF THE INVENTION

[0002] The present invention relates generally to the fabrication ofintegrated circuits on substrates. More particularly, the inventionrelates to a low temperature method for producing a low dielectricconstant (low κ) silicon carbide film utilizing organosilanes undercertain process regimes, which is useful as a low κ anti-reflectivecoating.

BACKGROUND OF THE INVENTION

[0003] Consistent and fairly predictable improvement in integratedcircuit design and fabrication has been observed in the last decade. Onekey to successful improvements is the multilevel interconnecttechnology, which provides the conductive paths between the devices ofan integrated circuit (IC) device. The shrinking dimensions of features,presently in the subquarter micron and smaller range, such as horizontalinterconnects (typically referred to as lines) and verticalinterconnects (typically referred to as contacts or vias; contactsextend to a device on the underlying substrate, while vias extend to anunderlying metal layer, such as M1 M2, etc.) in very large scaleintegration (VLSI) and ultra large scale integration (ULSI) technology,has increased the importance of reducing capacitive coupling betweeninterconnect lines in particular. In order to further improve the speedof semiconductor devices on integrated circuits, it has become necessaryto use conductive materials having low resistivity and low κ (dielectricconstant less than 7.0) insulators to reduce the capacitive couplingbetween adjacent metal lines. The need for low κ materials extends tobarrier layers, etch stops, and anti-reflective coatings used inphotolithography. However, typical barrier layer, etch stop, andanti-reflective coating materials have dielectric constants that aresignificantly greater than 7.0 that result in a combined insulator thatdoes not significantly reduce the dielectric constant. Thus, bettermaterials are needed for barrier layers, etch stops, and anti-reflectivecoatings in the low κ substrates.

[0004] With the change in circuit density, additional process changesare needed. For instance, efforts are being made to improve thephotolithography processes for more precise pattern etching.Photolithography is a technique used in making integrated circuits thatuses light patterns and typically organic polymers (photoresistmaterials) to develop fine-scaled patterns on a substrate surface.Photoresist materials typically include, for example, naphthoquinonediazides. In many instances, to properly process the substrate withphotolithography and avoid unwanted patterning, the high reflectivity ofthe layer to be patterned must be ameliorated so light ray reflection isreduced. Reflectivity is usually expressed as a percentage of a knownstandard, such as bare silicon, having a value of 100%. Extraneousreflections from underlying layers can be reflected to the photoresistand expose the photoresist in undesired areas. Any unwanted exposure candistort the lines, vias, and other features intended to be formed. Thereflectivity of damascene structures, discussed below, has increased theneed for better photolithography processes.

[0005] With multi-layer structures and the increased use of dielectrics,increased reflectivity has contributed to imprecise etching. Dielectriclayers are naturally translucent to the ultraviolet light used to exposethe photoresist. Thus, multi-level use of dielectrics in the damascenestructures results in increased and unwanted reflections. As a result,an anti-reflective coating (ARC) is deposited over the layer to beetched, where the ARC is a thin sacrificial layer that has a lowerreflectivity than the underlying layer and is etched by the same orsimilar chemistries that are used to etch the underlying layer. The ARCreduces or eliminates the extraneous reflections so that improvedfeature dimensions and accuracy can be more closely spaced, leading tothe increased current density desired for ULSI circuits.

[0006] ARC materials can be organic or inorganic, as described in U.S.Pat. No. 5,710,067, which is incorporated by reference herein. OrganicARCs include spin-on polyimides and polysulfones, among other materials,and are generally more expensive and require more complex processingthan inorganic ARCs. Inorganic ARCs include silicon nitride, siliconoxynitride, α-carbon, titanium nitride, silicon carbide, and amorphoussilicon. Prior to the present invention, inorganic ARCs typically werecharacterized by a high κ value and were not compatible with low κstructures. Use of a high κ ARC partially negates the advantage ofchanging to low κ materials in that it adds a high κ material to a stackof otherwise low κ layers. In some applications, the high κ ARC can beremoved from the substrate, but the removal adds complexity to theprocessing. Organic ARCs can be used, but they are generally moreexpensive and require additional processing.

[0007]FIG. 1 shows a representation of a substrate with a positivephotoresist deposited over a dielectric, as part of the photolithographyprocessing. A positive photoresist develops in the areas exposed tolight, whereas a negative photoresist develops in the areas not exposedto light. The integrated circuit 10 includes an underlying substrate 12having a feature 11, such as a contact, via, line, or trench. In thispatent, “substrate” is used to indicate an underlying material, and canbe used to represent a series of underlying layers below the layer inquestion, such as a barrier layer. A barrier layer 13 may be depositedover the substrate, followed by a dielectric layer 14. The dielectriclayer may be un-doped silicon dioxide also known as un-doped siliconglass (USG), fluorine-doped silicon glass (FSG), or some other low κmaterial. In this example, an ARC 15 is deposited over the dielectric,followed by a photoresist layer 19.

[0008] The purpose of the ARC is to reduce or eliminate any reflectedlight waves, typically, by adjusting three aspects of the ARC material—arefraction index (n), an absorption index (k, distinguished from the “κ”of a “low κ” dielectric), and the thickness (t) of the ARC to create aphase cancellation and absorption of reflected light. Typically, therequired n, k, and t values depend on the thickness and properties ofthe underlying layer and need adjustment for each particularapplication. A computer simulation program, such as one entitled “ThePositive/Negative Resist Optical Lithography Model”, v. 4.05, simulatesthe effect on the n, k, and t values and the reflectivity of theparticular layers. The results are analyzed and are typically followedby actual testing and reviewing the results through scanning electronmicroscopy (SEM) techniques. A proper combination at the various valuesof n, k, and t is chosen to reduce the reflected light for thatapplication. Because the values of n, k, and t are dependent on eachapplication and each substrate thickness, the proper selection may betime consuming and onerous. In addition, the selection may be onlyapplicable to narrow thickness ranges of the underlying layers which maycause additional difficulties in the repeatability of the depositionprocess from substrate to substrate.

[0009]FIG. 2 is a schematic of the photolithography process in which alight source 23 emits light, such as ultraviolet light, through apatterned template (mask) 21 that defines the pattern of light that willbe projected onto the photoresist layer 19, ultimately resulting in apatterned substrate. The light causes the photoresist in the exposedarea 25 to typically change its solubility to organic solvents, forinstance, when exposed to violet light. Thus, the exposed areas can beremoved by soaking or otherwise cleaning the exposed areas whileretaining the unexposed areas.

[0010]FIG. 3 is a schematic of the substrate with the feature 27 formedthereon using the etching process. The remainder of the photoresist hasbeen removed, the feature has been etched to the appropriate level, andthe substrate is prepared for a subsequent process such as thedeposition of a liner, dielectric, conductor, or other layer(s).

[0011] Traditional deposition/etch processes for forming interconnectshas also been improved with the higher circuit density to obtain moreprecise pattern etching. Thus, new processes are being developed. Forinstance, the traditional method of forming the circuit was depositingblanket layers of a conductor, etching the conductor to pattern thefeatures, and then filling the features with dielectric materials. Withthe emphasis on increased circuit density, the process has been somewhatreversed by depositing dielectric layers, etching the dielectric layersto form the features, and filling the features with conductive materialto form the vias, lines, and other features. The current trend is to usea damascene structure. In a dual damascene structure, the dielectriclayer is etched to define both the contacts/vias and the interconnectlines in multi-layered substrates. Metal is then inlaid into the definedpattern and any excess metal is removed from the top of the structure ina planarization process, such as chemical mechanical polishing (CMP).

[0012]FIG. 4 shows one example of a dual damascene structure. Twopredominate schemes currently are used to develop a dual damascenestructure, where lines/trenches are filled concurrently withvias/contacts. In a “counterbore” scheme, the integrated circuit 10includes an underlying substrate 12, which may include a series oflayers deposited thereon and in which a feature 11 has been formed. Abarrier layer 13 may be deposited over the substrate, followed by adielectric layer 14. A liner 22 may be needed, which typically is Ta,TaN, Ti, TiN, and other materials. The dielectric layer may be un-dopedsilicon dioxide also known as un-doped silicon glass (USG),fluorine-doped silicon glass (FSG), or some other low κ material. A lowκ etch stop 16, such as α-C, α-FC, parylene, AF₄, BCB, PAE, oxynitrideor silicon carbide, is then deposited on the dielectric layer 14 to athickness of about 200 Å to about 1000 Å. The etch stop material istypically a material that has a slower etching rate compared to thedielectric layer that is etched and allows some flexibility in theetching process in insuring that a predetermined depth is reached. Insome well characterized etching processes, the etch stop may beunnecessary. Another dielectric layer 18 is deposited over etch stop 16to a thickness of about 5,000 Å to about 10,000 Å. An ARC 15, similar tothe ARC 15 of FIG. 1, is deposited on the dielectric layer 18, followedby a photoresist layer (not shown), similar to photoresist layer 19shown in FIG. 1. The photoresist layer is exposed to form a pattern forthe via/contact 20 a, using conventional photolithography. The layersare etched using conventional etch processes, such as using fluorine,carbon, and oxygen ions to form the via/contact 20 a, and thephotoresist layer is removed. Another photoresist layer is deposited andexposed to pattern the line/trench 20 b, the layer(s) are etched to formthe line/trench 20 b, and the photoresist layer is removed. A conductivematerial 20 is then deposited simultaneously in both the via/contact 20a and the line/trench 20 b. Once the conductive material 20 has filledthe feature(s), another barrier layer 24 may be deposited to helpprevent diffusion of the conductor, such as the copper, for the nextseries of layers, if applicable.

[0013] The other predominate scheme for creating a dual damascenestructure is known as a “self-aligning contact” (SAC) scheme. The SACscheme is similar to the counterbore scheme, except that a photoresistlayer is deposited over the etch stop 16 prior to the deposition of thedielectric layer 18. The etch stop 16 is etched to form a pattern for avia/contact 20 a. The photoresist layer is removed and the dielectriclayer 18 and ARC 15 are then deposited over the etch stop, followed byanother photoresist layer deposited on the ARC 15. The photoresist isthen exposed to form the pattern for the line/trench 20 b, theline/trench 20 b and the via/contact 20 a are etched simultaneously, andthe photoresist layer is removed. Conductive material 20, and ifdesired, another barrier layer 24, are then deposited. These structuresare exemplary for a dual damascene structure and others, such as somedescribed below, may be more appropriate for the particular application.

[0014] The reflectivity of such multilevel structures as a damascenestructure has raised the needed level of performance of ARC materials.Prior to such structures, the layer to be etched was typically above asingle metal layer which is not transparent to the light exposure. Thus,the unwanted photoresist exposure from underlying layers wassubstantially limited to the single metal layer under the photoresist.However, in damascene and other structures, an increased number oflayers above the conductor layer are now used with multilevelpatterning. The dielectric layer(s) and other layers beside theconductor layer are comparatively transparent to the exposure light andthus more levels of reflections can hinder the photolithographyprocessing of the upper layer. For instance, lines and vias/contacts mayappear in the substrate at different levels. Light reflected from thedifferent features at the different levels result in different reflectedlight patterns back to the photoresist layer and unless corrected maycause the unwanted exposure on the photoresist described above.

[0015] Thus, with the decreasing feature sizes, the emphasis on low κstacks, the use of copper, and the complex dual damascene structures,new methods and materials are needed to provide improved ARCcharacteristics. Silicon nitride and oxynitride have been typicalmaterials used for an ARC, but have a relatively high dielectricconstant (dielectric constant greater than 7.0) and may significantlyincrease the capacitive coupling between interconnect lines. Thecapacitive coupling may lead to cross talk and/or resistance-capacitance(RC) delay, i.e., the time required to dissipate stored energy, thatdegrades the overall performance of the device. Additionally, siliconnitride and oxynitride have relatively poor diffusion resistancecompared to the material of the present invention.

[0016] In searching for new materials, others have recognized somepotential in silicon carbide (SiC) for some applications. But to theknowledge of the inventors, no source has adequately sought anddeveloped a suitable ARC, barrier layer, and etch stop, using SiC. Somesources, including U.S. Pat. No. 5,710,067 to Foote, et al., above, havenoted or suggested silicon carbide in some form as an ARC. To theknowledge of the inventors, silicon carbide that has been produced usingthese traditional methods has not been effective in meeting the newprocess requirements in low κ structures. For instance, the disclosedchemistry of U.S. Pat. No. 5,591,566 to Ogawa, which patent isincorporated herein by reference, uses separate sources of silicon,carbon, and hydrogen. This more traditional approach results in a higherκ than is desirable for the low κ emphasis of the ULSI efforts,especially in damascene structures. Another example, disclosed in U.S.Pat. No. 5,360,491 to Carey, et al., which is also incorporated hereinby reference, requires a conversion to a crystalline silicon carbide,denoted as β-SiC.

[0017] Another reference referring to SiC is U.S. Pat. No. 4,532,150 toEndo et al., which is incorporated herein by reference, wherein Endorefers to a specific formulation of Si_(x)C_(1-x) in which x is apositive number of 0.2 to 0.9 for providing SiC to a substrate surface.Endo provides no disclosure of SiC as a barrier layer, etch stop, orARC, and the process parameters given in its examples are below thepreferred or most preferred parameters of the present invention. U.S.Pat. No. 5,465,680 to Loboda, incorporated herein by reference,discloses a SiC film in a CVD chamber, but fails to produce the film atlow temperatures less than about 600° C. Another reference, U.S. Pat.No. 5,238,866 to Bolz, et al., also incorporated herein by reference,uses methane, silane, and phosphine to create a hydrogenated siliconcarbide coating for use in the medical field, having an improvedcompatibility with blood. However, none of these references contain adisclosure for SiC with the following process regimes used as a barrierlayer, etch stop, or a low κ ARC.

[0018] Therefore, there is a need for an improved process using siliconcarbide as a low κ ARC for ICs, especially in a damascene structure andespecially a SiC material that has set values for n, k, and thethickness of the SiC layer without necessitating experimentation for theproper values for each application.

SUMMARY OF THE INVENTION

[0019] The present invention generally provides a process for depositingsilicon carbide using a silane-based material with certain processparameters that is useful for forming a suitable ARC for ICapplications. The same material may also be used as a barrier layer andan etch stop, even in complex damascene structures and with highdiffusion conductors such as copper. Under certain process parameters, afixed thickness of the silicon carbide may be used on a variety ofthicknesses of underlying layers. The thickness of the silicon carbideARC is substantially independent of the thickness of the underlyinglayer for a given reflectivity, in contrast to the typical need foradjustments in the ARC thickness for each underlying layer thickness tomaintain a given reflectivity.

[0020] A preferred process sequence for forming a silicon carbideanti-reflective coating on a substrate, comprises introducing silicon,carbon, and a noble gas into a reaction zone of a process chamber,initiating a plasma in the reaction zone, reacting the silicon and thecarbon in the presence of the plasma to form silicon carbide, anddepositing a silicon carbide anti-reflective coating on a substrate inthe chamber.

[0021] Another aspect of the invention includes a substrate having asilicon carbide anti-reflective coating, comprising a semiconductorsubstrate, a dielectric layer deposited on the substrate, and a siliconcarbide anti-reflective coating having a dielectric constant of lessthan about 7.0 and preferably about 6.0 or less.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] So that the manner in which the above recited features,advantages and objects of the present invention are attained and can beunderstood in detail, a more particular description of the invention,briefly summarized above, may be had by reference to the embodimentsthereof which are illustrated in the appended drawings.

[0023] It is to be noted, however, that the appended drawings illustrateonly typical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

[0024]FIG. 1 is a schematic of photoresist material on an ARC in asubstrate.

[0025]FIG. 2 is a schematic of a light exposing the photoresist of FIG.1.

[0026]FIG. 3 is a schematic of the substrate of FIGS. 1 and 2, etchedand prepared for subsequent deposition in the feature.

[0027]FIG. 4 is a schematic of an exemplary damascene structure.

[0028]FIG. 5 is a FTIR of the SiC of the present invention, indicating aparticular bonding structure.

[0029]FIG. 6 is a FTIR of a previous SiC, indicating a bonding structuredifferent than the SiC of the present invention.

[0030]FIG. 7 is a graph of a dielectric constant compared to arefraction index for various materials.

[0031]FIG. 8 is a graph of the refraction index compared to theabsorption index for two materials, showing that the SiC of the presentinvention can be tuned to different index values.

[0032]FIG. 9 is a schematic of a stack of layers using the SiC of thepresent invention as a barrier layer, an etch stop, and an ARC.

[0033]FIG. 10 is a simulation graph of reflectivity contours of theembodiment of FIG. 9.

[0034]FIG. 11 is a line drawing of a scanning electron microscopyphotograph, showing a patterned photoresist layer using the ARC of thepresent invention as an upper layer.

[0035]FIG. 12 are FTIR results of a moisture test of the SiC of thepresent invention, when the SiC ARC is also used as a moisture barrier.

[0036]FIG. 13 is an alternative embodiment of FIG. 9, using the etchstop as the ARC without using an ARC upper layer.

[0037]FIG. 14 is a reflectivity map of the embodiment of FIG. 13,showing the thicknesses of the upper dielectric layer compared to theetch stop.

[0038]FIG. 15 is a reflectivity map of the embodiment of FIG. 13,showing the thicknesses of the etch stop compared to the lowerdielectric layer under the etch stop.

[0039]FIG. 16 is an alternative embodiment of FIGS. 9 and 13, withoutthe etch stop and using the barrier layer as the ARC.

[0040]FIG. 17 is a reflectivity map of the embodiment of FIG. 16,showing the thicknesses of the dielectric layer above the barrier layercompared to the barrier layer, using the barrier layer as an ARC.

[0041]FIG. 18 is another embodiment similar to the embodiment of FIG. 16with the addition of a SiC ARC below the photoresist layer.

[0042]FIG. 19 is a reflectivity map of the embodiment of FIG. 18,showing the thickness of the ARC compared to the thickness of thedielectric layer under the ARC.

[0043]FIG. 20 is a graph of copper diffusion into the SiC material ofthe present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

[0044] The present invention provides a SiC material, formed accordingto certain process regimes, useful as an ARC for an IC. The samematerial may also be used as a barrier layer and/or etch stop, andparticularly for an IC using high diffusion copper as a conductivematerial. The invention also provides processing regimes that includesusing an organosilane as a silicon and carbon source, perhapsindependently of any other carbon source or hydrogen source necessary toproduce the SiC and perhaps in the absence of a substantial amount ofoxygen. The process regimes also include the presence of a noble gas,such as helium or argon, and certain temperatures, pressures, poweroutputs in a plasma enhanced chemical vapor deposition chamber toproduce the SiC of the present invention. This particular SiC materialmay be especially useful in complex structures, such as a damascenestructure.

[0045] Table 1 below shows some of the general requirements for an ARC.Because the SiC, as explained below, may be used in multiple functions,Table 1 shows the desirable aspects of at least three of the uses of theSiC of the present invention as an ARC, a barrier layer, and an etchstop. TABLE 1 DESIRABLE CHARACTERISTICS OF ARC/BARRIER/ETCH STOPAnti-Reflective Coating Indexes n, k Multi-application suitabilityMulti-purpose use Low κ retained for particular n, k Stable andrepeatable Elimination of undesired reflections Multiplephotolithography uses Good Barrier Property to Copper Good Adhesion NoCopper Diffusion at 400°- 450° C. Annealing Stage High Etch Selectivitywith respect Etch Stop >20:1 to USG/FSG/Other Low κ Dielectric MaterialsLower Dielectric Constant Overall Reduction in Effective DielectricConstant (K_(eff)) in IMD Damascene Stacks Good Electrical PropertiesHigh Breakdown Voltage Low Leakage Productivity/ManufacturabilityProcess Stability and Particle Control In-situ Process for ThroughputImprovement, e.g., USG Deposi- tion with Etch Stop Layer Deposition

[0046] If the SiC is used as an ARC, desirable characteristics wouldinclude the low κ aspect described above as well as a suitablerefraction index “n” combined with an absorption index “k” and athickness “t” of the ARC to obtain a low reflectivity below about 5%,although other values may be selected, so that the coating could be usedin multiple applications without necessitating adjustments andvariations for each application, as is typically needed, prior to thepresent invention. The process to produce the SiC should be stable andrepeatable for manufacturing consistency.

[0047] Because the ARC may remain on the substrate because of its low κattributes, it may also function as a barrier layer between, forinstance, an underlying dielectric and a conductor material, such ascopper. Thus, the barrier properties may be important in such instances.Adhesion between the layers is important to reduce delamination betweenthe layers and, in some instances, to reduce capacitance and resistancebetween the layers. When the ARC is used as a barrier, the materialshould also have no substantial diffusion at a substrate annealingtemperature of, for example, 400°-450° C. The term “no substantial”diffusion is intended to be a functional term, such that any actualdiffusion into the layer is less than would affect the ability of thelayer to function as a barrier layer and/or etch stop. For instance, theSiC of the present invention limits the diffusion to about 250 Å. Thecopper diffusion may impair the desired current and voltage paths andcontribute to cross talk. Because of the decreasing feature size, asdescribed above, the lower the dielectric constant, preferably less than7.0, the lower the probability for cross talk and RC delay whichdegrades the overall performance of the device. A low κ material isdefined herein as a material having a dielectric constant lower thanthat of silicon nitride (dielectric constant of greater than or equal to7.0), which has traditionally been used as a barrier layer material.Related to the low dielectric value is the “effective” dielectricconstant, which is a composite dielectric constant of the substratestack with multiple levels. The effective dielectric constant is basedon such factors as the layer thicknesses, layer dielectric constants,spacing between features, and feature dimensions. Commercially availablesoftware, such as “Rafael” by Avant Corporation may be used to calculatethe predicted effective dielectric constant. For instance, a typicalvalue of a low κ dielectric layer is about 2.7. A SiN layer may have a κvalue of 7.0. Using the SiN material with the low κ material wouldincrease the effective κ value of the composite and offset some of theadvantage of using the low κ dielectric material. In comparison, usingthe SiC of the present invention with a κ value of less than 5,preferably about 4.2, allows more benefit from using low κ dielectricmaterial to be obtained. A desirable effective dielectric constant valuefor the composite structure would be about 5.0 or less, most preferably3.0 or less.

[0048] Because the SiC may be used in a damascene structure and functionas a dual purpose ARC and etch stop as discussed below in oneembodiment, it would be beneficial to also have suitable etch stopcharacteristics, such as an etch selectivity ratio of 20 to 1 or greaterwith respect to USG, FSG, or other low κ dielectric materials.Additionally, the material should have a high breakdown voltage of 2 MVor more, i.e., the voltage gradient at which the molecules breakdown toallow harmful passage of electrical current. The SiC should also have alow leakage characteristic through the layer, i.e., a low stray directcurrent that capacitively flows through the material.

[0049] Another desired characteristic from a commercial standpoint isthat the deposition of the material may be performed in situ, i.e., in agiven chamber, such as in a plasma chamber, or in a system, such as anintegrated cluster tool arrangement, without exposing the material tointermediate contamination environments. This aspect may be particularlyimportant with a copper conductor, because of its rapid susceptibilityto oxidation.

[0050] Table 2 shows the process parameters of the present inventionused in a 200 mm wafer deposition reactor that allows the SiC materialto be used as an ARC, as well as a barrier layer and an etch stop. Inthe preferred embodiments, the silicon and carbon were derived from acommon compound, such as a silane-based compound. However, the carboncould be supplemented with other compounds, such as methane. Withoutlimitation, suitable silane-based compounds could include: methylsilane(CH₃SiH₃), dimethysilane ((CH₃)₂SiH₂), trimethylsilane ((CH₃)₃SiH),diethylsilane ((C₂H₅)₂SiH₂), propylsilane (C₃H₈SiH₃), vinyl methylsilane(CH₂═CH)CH₃SiH₂), 1,1,2,2-tetramethyl disilane (HSi(CH₃)₂—Si(CH₃)₂H),hexamethyl disilane ((CH₃)₃Si—Si(CH₃)₃), 1,1,2,2,3,3-hexamethyltrisilane (H(CH₃)₂Si—Si(CH₃)₂—SiH(CH₃)₂), 1,1,2,3,3-pentamethyltrisilane (H(CH₃)₂Si—SiH(CH₃)—SiH(CH₃)₂), and other silane relatedcompounds. For the purposes of this invention, the term “organosilane”as used herein includes any silane-based compound having at least onecarbon atom attached, including the preceding list, unless otherwiseindicated. In Table 2, the compounds used were trimethylsilane andmethylsilane. A noble gas, such as helium or argon, was present and mayassist in stabilizing the process, although other gases could be used.

[0051] The inventors have discovered that the process regimes describedbelow provide a SiC material that meets at least some of thecharacteristics of Table 1 of an ARC, as well as a barrier layer and/oretch stop. Using the process regimes, the SiC has a low dielectricconstant of less than about 7.0 and preferably about 6.0 or less.Importantly, the SiC properties described herein enable a thinner layerto be deposited. An effective substrate dielectric constant of thepresent invention may be about 5.0 or less. This effective dielectricconstant meets the needs of a suitable copper-based IC and contrastswith silicon nitride material described above. As an upper layer for anARC, the SiC, in one embodiment allows a diverse range of underlyingdielectric thicknesses without needing to adjust the SiC ARC thickness.Also, in a damascene structure, the SiC of the present invention may beused as a combination etch stop and ARC, without needing the upper ARClayer, typical in photolithography. This particular SiC material also issuitable for use as a low κ, etch stop material. A low κ material isdefined herein as a material having a dielectric constant lower thanthat of silicon nitride (dielectric constant of greater than or equal to7.0). A low κ etch stop material is defined herein as an etch stopmaterial having a dielectric constant lower than that of silicon nitrideand having a relative oxide to etch selectivity of 20 to 1 or greaterrelative to the dielectric material. This ratio allows greater controlover the etching process and is particularly useful when etching complexstructures, such as a damascene structure. Furthermore, the SiC materialof the present invention has a high resistance to copper diffusion withtest data showing that the copper diffusion limit is about 200 to 250 Ådeep in the barrier layer. In one embodiment, shown in FIGS. 15 and 16,the ARC may be the barrier layer functioning as the ARC without the etchstop. TABLE 2 Parameter Range Preferred Most Pref. Silicon (3MS or 10-1000  30-500  50-200 MS-sccm) Carbon (3MS or above above aboveMS-sccm) Noble (He or Ar-sccm)  50-5000  100-2000  200-1000 Press.(Torr)  1-12  3-10  6-10 RF Power (Watts)  100-1000 300-700 400-600Power Density  0.7-14.3  4.3-10.0 5.7-8.6 (Watts/cm) Freq. (MHz) 13.5613.56 13.56 Temp. (C.) 100-450 200-400 300-400 Spacing (Mils) 200-600300-600 300-500

Example Process—ARC/Barrier Layer/Etch Stop

[0052] To create an ARC that may also function as a barrier layer and/oretch stop, a silicon source such as trimethylsilane or methylsilane issupplied to a plasma reactor, specifically a reaction zone in thechamber that is typically between the substrate surface and the gasdispersion element, such as a “showerhead”, commonly known to those withordinary skill in the art. For a typical commercial plasma enhancedchemical vapor deposition (PECVD) chamber such as manufactured byApplied Materials, Inc. of Santa Clara, Calif., a silicon source flowrate of about 30 to 500 standard cubic centimeters (sccm) is used. Thesequence and operation of a commercial PECVD chamber are well known andneed no explanation for the present invention process regimes. Thecarbon is derived from the trimethylsilane or methylsilane, independentof other carbon sources. The reaction occurs without a substantialsource of oxygen introduced into the reaction zone. In conjunction withthe silicon and carbon sources, a noble gas, such as helium or argon, isflown into the chamber at a rate of about 100 to 2000 sccm. The chamberpressure is maintained between about 3 to 10 Torr. A single 13.56 MHz RFpower source applies about 300 to 700 watts with a power density ofabout 4.3 to 10 watts/cm² to the anode and cathode to form the plasma inthe chamber with the silane-based gas. The substrate surface temperatureis maintained between about 200° to 400° C., during the deposition ofthe SiC. The gas dispersion from a gas dispersion element, such as a“showerhead”, is dispersed at a showerhead to substrate spacing distancebetween about 300 to 600 mils.

[0053] For a more optimal, designated “most preferred,” process regime,the trimethylsilane or methylsilane flow rate is adjusted to about 50 to200 sccm, the helium or argon flow rate to about 200 to 1000 sccm, thechamber pressure to about 6 to 10 Torr, the RF power to about 400 to 600watts with a power density of about 5.7 to 8.6 watts/cm², the substratesurface temperature maintained between about 300° to 400° C., and ashowerhead to substrate spacing of about 300 to 400 mils, as shown inTable 2.

[0054] The characteristics developed by the preferred and most preferredprocess regimes differ from the generally accepted silicon carbidecharacteristics. At these parameters, a different bonding structureoccurs in the SiC of the present invention, shown in FIG. 5, compared toa prior SiC, shown in FIG. 6, described below. The charts are FourierTransform Infrared (FTIR) charts, one of the standard laboratory testsfor indicating the bonding structure, as would be known to those withordinary skill in the art and needs no detailed explanation. The variouspeaks at various wave numbers are structure specific and this graph isindicative of the particular interstitial bonding structure.

[0055]FIG. 5 shows a FTIR for the SiC of the present invention. Usingthe most preferred range of process parameters of Table 2 withtrimethylsilane, the deposition resulted in a bonding structurecontaining CH₂/CH₃, SiH, SiCH₃, Si—(CH₂)n, and SiC. FIG. 6 showscomparative results with a prior SiC material deposited using silane andmethane. As can be seen, there is no corresponding peak for Si—(CH₂)nand even the peak for SiCH₃ is not as noticeable. The SiC of the presentinvention has yielded these unexpected results in providing betterARC/barrier layer/etch stop performance than previous known depositionsof SiC. These characteristics allow the SiC to be used in the multiplecapacities disclosed herein.

[0056] FIGS. 7-20 show various characteristics of the SiC ARC of thepresent invention. FIG. 7 is a graph of test results, using a standard633 nm wavelength of exposure light, comparing different materials andtheir dielectric constants versus the refraction index. The x-axisrepresents the refraction index, n, discussed above. A lower value onthe x-axis is preferred and results in better optical quality andtransparency. The y-axis represents the dielectric constant. A lowervalue on the y-axis is preferred to obtain a “low κ” substrate stack.For instance, SiN typically has an n value of about 2.0 and a dielectricconstant value of 7.3, unsuitable for the low κ applications. A currentstate-of-the-art ARC is DARC™, a type of silicon oxynitride, but thedielectric constant is about 8.5-9.0 with a n of about 2.2 at a 248 nmwavelength exposure. The preferred SiC of the present invention has adielectric constant of about 4.2.

[0057] The SiC#1 corresponds to test results using the traditionalchemistry for producing SiC such as is described in U.S. Pat. No.5,591,566 to Ogawa, discussed above, particularly using a silane with aseparate methane/ethane/propane and diatomic hydrogen. This SiC has an nvalue of about 2.4, and a dielectric constant of about 7.8, undesirablefor deposition in low κ devices. In-house test results that varied theprocess parameters of this traditional SiC chemistry still did notproduce the results that were obtained by changing to the chemistry ofthe present invention, described herein.

[0058] SiC#2 is one SiC deposited using the chemistry of the presentinvention. The n value is about 2.3 and the dielectric constant is about5.1, which are much better than the SiC#1 produced by traditionalprocessing, above. Using the most preferred parameters described abovein Table 2, the SiC#3 produced better optical characteristics, namely,an n value of about 1.9 at the 633 nm exposure wavelength of FIG. 6 witha dielectric constant of about 4.2. Thus, optically and resistively, theSiC of the present invention is suitable for the current emphasis on lowκ structures that can be used as an ARC as well as a barrier layer andan etch stop. Importantly, the SiC of the present invention, in contrastto the traditional high κ SiC, need not be removed from the layer afterthe photoresist has been exposed and the substrate etched in order topreserve the low κ characteristics of the stack of layers, resulting inless processing steps.

[0059]FIG. 8 is a graph of the refraction index n compared to theabsorption index k for two materials, using a 248 nm exposure wavelengthtypically used in photolithography processing, showing that the SiC ofthe present invention can be tuned to different n and k values and iscompared with a silicon oxynitride ARC. The silicon oxynitride ARC has asteep slope of about 70°, a high dielectric constant of about 9, and isdifficult to control the respective n and k values because of the rapidincrease in k with a small change in n. By comparison, the SiC of thepresent invention with a dielectric constant of about 4.5, has a flattercurve, approximating a 35° upward slope of the line on the graph, sothat an increase in n results in a comparative increase in k on thegraph, and shows a more controllable process. A higher absorption indexis desirable to better absorb the extraneous reflections, but inobtaining the higher absorption indexes, the dielectric constantincreases as the line slopes upward. Thus, there is a balance betweenthe desired optical properties and dielectric constant for theparticular embodiment desired. Through experiments, the inventorsbelieve that a suitable value for the SiC of the present invention andone that is most preferred, having a relatively low dielectric constantand a stable process regime, is about 2.2 for an n value at the 248 nmexposure wavelength of FIG. 8 and about 0.4 for a k value. In the graph,the relationship between the n and k indexes at the 248 nm exposurewavelength appears linear and is approximated by the formula below usingthe process parameters herein disclosed:

k/0.65+1.57=n

[0060] The absorption index k may vary with a range of between about 0.2to about 1.0, and generally may be between about 0.3 and 1.0 forcommercial uses in photolithography. The above formula is representativeof the n and k characteristics of the SiC of the present invention andcan be readily converted for different exposure wavelengths. Beginningat the x-axis value in FIG. 8, the slope of the SiC n and k relationshipmay vary from about 20° to about 60° with the slope shown as about 35°.

[0061] Importantly, the dielectric constant of the silicon oxynitrideARC is about double that of the SiC and yet the SiC has about the same nand k values. Stated differently, using the SiC of the present inventioncan approximate the optical qualities of the silicon oxynitride ARC andyet reduce the dielectric constant by about 50%. In a low κ stack oflayers, that difference is important.

[0062]FIG. 9 is a schematic of a stack of layers using the SiC of thepresent invention as a barrier layer, an etch stop, and an ARC. Thedielectric layer 60 has a contact 62, which may be a copper material. Abarrier layer 64 of SiC having a thickness of about 500 Å is depositedover the dielectric layer 60 and over the contact 62. A dielectric layer66, such as an USG layer with a thickness of about 5000 Å thick, isdeposited over the barrier layer. An etch stop 68, again of about 500 ÅSiC material, is deposited over the dielectric USG layer, followed byanother dielectric layer 70, which also may be an USG material having athickness of about 7000 Å. In this embodiment, an ARC 72 of SiC having athickness of about 600 Å is deposited over the previous USG layer, andis followed by a photoresist layer 74. As described in FIGS. 1-3, thephotoresist is exposed through a mask, the unwanted portions washedaway, the layers etched which produces features, and further layersdeposited such as liner, barrier, and conductive layers. Thethicknesses, number of layers, and arrangement could vary and theembodiment is exemplary.

[0063]FIG. 10 is a simulation graph of reflectivity contours forprojecting reflectivity values of different combinations of layerthicknesses, using a computer simulation program, entitled “ThePositive/Negative Resist Optical Lithography Model”, v. 4.05. Thesimulation graph is used to predict the substrate reflectivity atincremental rates, resulting is a reflectivity topography that maps theeffects on reflectivity of the thickness of one layer to the thicknessof an adjacent layer. In FIG. 10, each contour is set to increment by 2%with the lowest being 2% reflectivity and the highest being 16%reflectivity. In this figure, the x-axis is the thickness of theunderlying layer, i.e., the dielectric layer 70 in FIG. 9. The y-axis isthe SiC thickness used as an ARC, corresponding to the ARC 72 of FIG. 9.The goal of obtaining low reflectivity is to minimize the extraneousreflections from the substrate at the photoresist interface between, inthis instance, the photoresist layer and the ARC. An optimalreflectivity value is 0%, but Applied engineers have learned that areflectivity of less than about 7% provides commercially acceptableresults with a goal of about 5% or less being preferred to insurerepeatability of the photolithography processing. While in someembodiments a 10% reflectivity is acceptable, 10% reflectivity istypically a practical limit to the current size and density of featuresin the substrate. Thus, if the underlying layer thickness is known andis selected on the x-axis, the corresponding preferred ARC thickness onthe y-axis can be predicted by locating an ARC thickness having lessthan the chosen reflectivity, such as 5%. For instance, a dielectricthickness of about 6500 Å to about 6750 Å shown as range 76 in FIG. 10,will predictably need about 200 Å of ARC to meet the 5% or lessreflectivity criteria. However, such a narrow range of dielectricdeposition may be difficult to consistently produce and may not meetdevice requirements for electrical isolation of the circuit between thelayers. Furthermore, the 200 Å layer may be insufficient as a barrierlayer to copper if, for instance, copper was deposited on the ARC afteretching. Thus, while optically, the ARC layer would be sufficient, otherproperties, such as described above, may need consideration. In thisfigure, an ARC thickness of more than about 500 Å results in less than5% reflectivity across the range of dielectric layer thickness in thegraph. Conversely, if the dielectric layer thickness can be carefullycontrolled, then the ARC layer thickness can be varied or minimized. Forinstance, a dielectric thickness of about 6600 Å, plus or minus about100 Å or about 1.5%, can have an ARC thickness of 50 Å or more and meetthe optical parameters of 5% or less reflectivity. Thus, the SiC of thepresent invention satisfies the desire for a multiple purpose materialin providing a barrier layer, etch stop, and an ARC and satisfies thedesire for a multiple application material in that a single ARCthickness can meet the optical needs of multiple dielectric thicknessesfor a given reflectivity.

[0064] In a preferred embodiment, a layer with a preferred thickness ofabout 600 Å offers one of the lowest reflectivity values across theentire spectrum of the dielectric layer thicknesses, shown as value 78in the graph. Importantly, the inventors have discovered that, with theunique properties of the SiC of the present invention, an ARC can bedeposited that is substantially independent of the underlying layerthickness. The range may be about 500 Å to about 1000 Å or more, with apreferred thickness of about 600 Å, having a predicted reflectivity ofabout 2% or less, below the preferred 5% range. This discovery contrastswith the typical need to adjust the n, k, and t characteristics of theARC layer to the particular thickness of the underlying layer for eachapplication. Here, using the SiC of the present invention, the ARC layermay simply be a consistent deposition thickness of about 600 Å,regardless of the underlying layer thickness. The graph may be analyzedfor other appropriate ranges, as the particular application may finduseful.

[0065] The SiC ARC 72 of the present invention may also be used as apolish stop. After the stack is etched and the features filled withconductive material, some processing methods polish the upper surface ofthe substrate surface to remove excess conductive material and planarizethe upper surface to prepare for the next deposition, if applicable.Typically, the substrate is polished by a chemical mechanical polishing(CMP) process, well known to those in the field. The CMP process uses adifference in polishing rates between different materials to determinethe limit of polishing, for instance, as the CMP process encounters aunderlying polish resistant layer. With the present invention, the SiCARC 72 may be used as a polish stop. Because of the low κ of the SiCARC, the ARC will typically remain on the substrate and need not beremoved to maintain an effective low κ substrate. Thus, conductivematerial may be deposited over the ARC, filling the features. The CMPprocess then is used to remove any extra conductive material or anyother material above the SiC. As the CMP process determines a differencein the polishing rates when the process encounters the SiC ARC, then theCMP process may be discontinued.

[0066] Also, the SiC ARC material may be used as a moisture barrier. TheCMP process is typically a wet process. Because moisture can corrupt asubstrate circuit, some layer needs to be moisture resistant. If, forinstance, the SiC ARC is used as a polish stop, then as an upper layer,the SiC ARC would desirably act as a moisture barrier.

[0067]FIG. 11 is a line drawing of a scanning electron microscopyphotograph, showing a cross section of a patterned photoresist layer 74deposited over a SiC ARC 72 of the present invention. FIG. 11 shows thephotolithography results of such embodiments as shown in FIG. 9, wherethe ARC is considered the top layer of the substrate prior to thephotoresist layer deposition and photolithography processing. The widthof the line 80 in the photoresist layer 74 is about a quarter micron,representative of the current size of features. With the SiC ARC 72 ofthe present invention, the photolithography patterning of thephotoresist layer 74 resulted in even and straight lines 82, importantfor the ULSI reduced feature sizes. The patterning in the features wasuniform and had straight, square sidewalls 84, i.e., no standing waveeffects from extraneous light reflections, with a fully exposed bottom86 and square corner 88 without a substantial rounded “footing” in thecorner. The variation in minimum to maximum values of the photoresistwidth 90 between the lines is 5% or less, a standard acceptance rangefor processing. The repeatability from line to line is also shown. Thus,the uniformity of the patterned photoresist layer demonstrates that theSiC ARC of the present invention is able to produce a photolithographyprocessed substrate with small features and still retain a low κ value,in contrast to other ARC materials, such as the silicon oxynitride ARC,described above.

[0068]FIG. 12 shows the FTIR results of a moisture test of the SiCmaterial exposed to boiling water for a 30 minute period. The upper lineof the moisture results before the exposure is offset from the lowerline of the moisture results after the exposure to view both lines onthe same graph. Tests results show that the SiC of the present inventionacts as a moisture barrier throughout the CMP process and thus satisfiesthe moisture barrier aspect, as well. The moisture level is particularlynoted at wave number 1640, which is the H—OH peak, where the results aresubstantially the same, indicating substantially no moisture absorbed.

[0069]FIG. 13 is an alternative embodiment of FIG. 9, without using aseparate ARC, but relying on the properties of the SiC of the presentinvention between adjacent layers to function as an ARC, i.e., here theetch stop 68 between the dielectric layers 66 and 70. The layers andnumbers correspond to the arrangement described in FIG. 9, with thedifference being no ARC 72 under the photoresist layer 74. In thisembodiment, the thickness of the dielectric layer 70 above the SiC etchstop 68 is adjusted in conjunction with the thickness of the SiC etchstop 68 between the dielectric layers 66 and 70 for a projectedreflectivity. The thickness of the dielectric layer 66 is held constant.The photoresist layer 74 would be exposed as described above. Thebarrier layer 64 may be about 500 Å. However, the substrate would relyon the reflective and absorptive characteristics of the SiC etch stop 68below the upper dielectric layer 70. Thus, the thicknesses of the twolayers are interdependent for a given projected reflectivity. A properselection of the SiC etch stop thickness makes this arrangementsuitable, as shown in FIG. 14.

[0070]FIG. 14 is a reflectivity map of the embodiment of FIG. 13,showing the thicknesses of the upper dielectric layer 70 compared to theetch stop 68. The y-axis is the thickness of the dielectric layer 70 andthe x-axis is the thickness of the SiC etch stop 68. The axes arereversed from the reflectivity map of FIG. 10, because in thisembodiment the top layer is the dielectric layer 70. Similar to thediscussion in FIG. 10, the appropriate thicknesses may be selected forgiven reflectivity ratios, such as below about 5%. For example, an etchstop thickness of about 150 Å, plus or minus 50 Å, would opticallysatisfy the requirements for all the graphed thicknesses in FIG. 14 ofthe dielectric layer 70 and would have a reflectivity of less than about5%. However, a 150 Å SiC layer would be undesirably thin to alsofunction as a copper barrier layer. Factors, such as control factors inetch processing, or barrier properties may ultimately determine theproper thickness for an etch stop and whether alternative thicknessesfor the optical properties of an anti-reflective coating are needed.

[0071] Also, a SiC etch stop of about 720 Å thick could be used with atop dielectric layer thickness of about 6500 Å or about 7300 Å. Becausethe reflectivity pattern repeats in this zone, other layer thicknessesnot charted could be used and the thicknesses shown in FIG. 14 and othersimilar figures are typical of the thicknesses used in commercialembodiments. If a higher level of reflectivity were allowed, forinstance 6%, then an etch stop thickness of about 720 Å would alsosatisfy the optical requirements for reflectivity for all the graphedthicknesses on FIG. 14. Conversely, if the dielectric thickness wasfirst selected and a resulting etch stop thickness determined, then, forexample, a dielectric thickness of about 6600 Å and about 7400 Å withclose tolerances could allow an etch stop thickness of about 100 Å toabout 350 Å with a reflectivity of about 5% or less. Other values may bedetermined, using the contours of the figures. Importantly, theseexamples show that the thickness of the etch stop and the thickness ofthe dielectric layer adjacent the etch stop are to be considered withrespect to each other when the SiC, functioning as an ARC, is betweenthe dielectrics for a projected or chosen reflectivity.

[0072]FIG. 15 is another reflectivity map of the embodiment of FIG. 13,showing the thickness of the etch stop compared to the thickness of thelower dielectric layer under the etch stop, where the dielectric layer66 below the etch stop 68 is adjusted in conjunction with the thicknessof the etch stop 68 for a projected reflectivity. Here, the dielectriclayer 70 may remain a certain thickness, such as 7000 Å, while thethicknesses of the etch stop 68 and dielectric layer 66 are determinedfor a particular reflectivity. In FIG. 15, because the etch stop 68 isthe upper layer relative to the dielectric layer 66, the etch stopthickness is represented on the y-axis and the dielectric layer 66thickness is represented on the x-axis. For instance, with a 500 Å SiCetch stop, the thickness of the dielectric layer 66 could be about 4600Å or about 5400 Å to maintain a 5% or less reflectivity. However, thethickness of the dielectric layer 66 may change for a differentthickness of the dielectric layer 70. Thus, iterative solutions may berequired to find a thickness for each dielectric layer that meets thevarious process requirements and still collectively satisfy areflectivity goal, here of about 5% or less.

[0073]FIG. 16 is an alternative embodiment of FIGS. 9 and 13 without theetch stop, where the barrier layer 64 is used as the ARC. In someprocesses, the upper layer ARC 72 of the embodiment of FIG. 9 may not beused, as shown in FIG. 13. In still other processes, the etch stop 68 ofFIG. 13 may also not be used, as shown in FIG. 16. If the etch stop canbe eliminated, then the substrate processing throughput may be increasedwith fewer steps and a lower effective dielectric constant of thesubstrate may be obtained. The difficulty with eliminating the etch stopis the repeatability of the etching process and the timing of theetching so that undesired etching through typically the dielectriclayer(s) does not occur. However, if the process is well characterizedand has sufficient control, then the etch stop may not be used. Thelayers and numbers correspond to the arrangement described in FIGS. 9and 13, with the difference being no ARC 72 under the photoresist 74 andno etch stop 68. In this embodiment, the thickness of the dielectriclayer 66 is increased to compensate for the lack of the seconddielectric layer 70 so that the circuit is electrically isolated and maybe about 10,000 Å to about 12,000 Å thick. The dielectric layer 66thickness is adjusted in conjunction with the thickness of the SiCbarrier layer 64 between the dielectric layer 66 and the dielectriclayer 60 for a projected reflectivity. The photoresist 74 would beexposed as described above. However, the substrate would rely on thereflective and absorptive characteristics of the SiC barrier layer 64below the dielectric layer 66, where the thicknesses of the two layersare interdependent or independent, contingent upon the thickness(es)selected and the desired reflectivity. A proper selection of the SiCbarrier layer thickness makes this arrangement suitable, as shown inFIG. 17.

[0074]FIG. 17 is a reflectivity map of the embodiment of FIG. 16,showing the thicknesses of the dielectric layer 66 compared to the SiCbarrier layer 64, using the barrier layer as an ARC. In FIG. 17, becausethe dielectric layer 66 is above the barrier layer, the y-axisrepresents the dielectric layer thickness and the x-axis represents thebarrier layer thickness. Because other parameters may be considered,such as the ability of the dielectric layer to electrically isolate thecircuit, the dielectric layer thickness may be first selected and thebarrier layer thickness determined from the graph for a givenreflectivity. A preferred thickness of the SiC barrier layer when usedas an ARC, in this embodiment without the intervening etch stop, isabout 700 to about 800 Å. The preferred thickness yields a predicted 5%reflectivity or less for all graphed thickness of the dielectric layer.Thus, in this embodiment as well, the SiC of the present inventionprovides ARC optical results substantially independent of the dielectriclayer thickness.

[0075]FIG. 18 is another embodiment similar to the embodiment of FIG. 16with the addition of a SiC ARC 72 below the photoresist layer 74. Theetch stop 68 of FIG. 9 is not used in the embodiment of FIG. 18 and thedielectric layer 66 is typically thicker than the separate dielectriclayers of FIG. 9. The SiC barrier layer 64 is about 500 Å thick,although the thickness could vary. As shown in FIG. 19 below, thethickness of the dielectric layer 66 can vary without significantlyaffecting the reflectivity on the photoresist layer 74, when the SiC ARC72 thickness is appropriately selected. However, a typical thickness ofthe dielectric layer 66 may be about 10,000 Å to about 12,000 Å.

[0076]FIG. 19 is a reflectivity map of the embodiment of FIG. 18,showing the thickness of the ARC compared to the thickness of thedielectric layer under the ARC for a projected reflectivity. In FIG. 19,the ARC 72 thickness is represented on the x-axis and the dielectriclayer 66 thickness is represented on the y-axis. The reflectivity mapshows that with an ARC thickness of about 520 Å or greater, any of thegraphed thickness of the dielectric layer 66 may result in areflectivity of about 5% or less. A preferred thickness of the SiC ARCis about 600 Å. The pattern repeats, as in other reflectivity maps, andthus other thicknesses of the oxide and/or SiC layer could be determinedby extrapolation. Similar to the other embodiments discussed herein, theinventors have discovered that, with the unique properties of the SiC ofthe present invention, an ARC can be deposited that is substantiallyindependent of the adjoining layer thickness, for a particular projectedreflectivity. Here, using the SiC of the present invention, the ARClayer may be a deposition thickness of about 600 Å, regardless of theunderlying layer thickness to obtain a projected reflectivity of about5% or less. The graph may be analyzed for other appropriate ranges, asthe particular application may find useful.

[0077] Because the SiC of the present invention may be used in proximityto conductive materials, such a copper, that are prone to diffusionthrough adjacent layers, it is preferable that the SiC be diffusionresistant, as well. FIG. 20 shows the test specimen diffusion results,where the lower curve shows the copper content, showing the diffusionresistance to copper of the SiC ARC material of the present invention.The test specimen was a substrate with a 200 Å layer of copper, a 800 Ålayer of SiC deposited on the copper, and a 1000 Å layer of oxidedeposited on the SiC. Starting with the y-axis, FIG. 20 shows a value 46of approximately 3××10¹⁷ atoms per cubic centimeter (atoms/cc) at adepth of 0 Å from the surface of the 1000 Å oxide layer. This valuereduces to value 48 of about 1×10¹⁶ atoms/cc through the oxide layer andinto the 800 Å SiC layer at a combined depth of about 1570 Å, before thecopper diffusion becomes noticeable. The copper diffusion level thenrises logarithmically for the next 230 Å to a value 50 of approximately3×10²¹ atoms/cc at the copper to copper barrier interface. Thus, thelevel of copper reduces by approximately four orders of magnitude, i.e.,{fraction (1/10,000)}, within about 200 Å to 250 Å of the interface.This decrease in copper diffusion shows the effectiveness of the SiCmaterial of the present invention.

[0078] The present invention further provides a substrate processingsystem having a plasma reactor including a chamber, a reaction zone inthe chamber, a substrate holder for positioning a substrate in thereaction zone, and a vacuum system. The processing system furthercomprises a gas/liquid distribution system connecting the reaction zoneof the vacuum chamber that supplies an silane-based compound, an inertgas, and an RF generator coupled to the gas distribution system forgenerating a plasma in the reaction zone. The processing system furtherincludes a controller comprising a computer for controlling the plasmareactor, the gas distribution system, the RF generator, and a memorycoupled to the controller, the memory comprising a computer usablemedium including a computer readable program code for selecting theprocess steps for depositing a low dielectric constant film with aplasma of an silane-based compound.

[0079] The processing system may further comprise in one embodimentcomputer readable program code for selecting the process steps fordepositing a barrier layer and/or etch stop of the silane-basedcompound, depositing a different dielectric layer, and optionallydepositing a capping passivation layer of the silane-based compound.

[0080] While foregoing is directed to the preferred embodiment of thepresent invention, other and further embodiments of the invention may bedevised without departing from the basis scope thereof, and the scopethereof is determined by the claims that follow. Furthermore, in thisspecification, including particularly the claims, the use of“comprising” with “a” or “the”, and variations thereof means that theitem(s) or list(s) referenced includes at least the enumerated item(s)or list(s) and furthermore may include a plurality of the enumerateditem(s) or list(s), unless otherwise stated. Also, any disclosure ofmethods, including the claims, are presented in a logical order, but arenot restricted to the sequence disclosed unless specifically stated.

What is claimed is:
 1. A substrate having a silicon carbideanti-reflective coating, comprising: a) a dielectric layer deposited onthe substrate; and b) the silicon carbide anti-reflective coating havinga dielectric constant less than 7.0.
 2. The substrate of claim 1,wherein the substrate has an effective dielectric constant of about 5 orless.
 3. The substrate of claim 1, wherein the silicon carbideanti-reflective coating inhibits copper diffusion from a copperinterface by about 3 orders of magnitude within about 300 Å or less fromthe interface.
 4. The substrate of claim 1, wherein the silicon carbideanti-reflective coating is produced by a process in a plasma reactorhaving a chamber comprising providing an organosilane flow rate ofbetween about 30 to about 500 sccm as a silicon and carbon source and anoble gas flow rate of between about 100 to 2000 sccm and furthercomprising reacting the silicon and the carbon in a chamber pressurerange of about 3 to about 10 Torr with an RF power source supplying apower density of about 4.3 to about 10.0 watts per square centimeter toan anode and cathode in the chamber and a substrate surface temperatureof between about 200° to about 400° C.
 5. The substrate of claim 1,wherein the silicon carbide anti-reflective coating has an absorptionindex, a refraction index, and a coating thickness and wherein thecombination of the indexes and thickness provide an anti-reflectivecoating for the substrate having a reflectivity of about 7 percent orless that is substantially independent of a layer thickness of adielectric layer adjacent the anti-reflective coating.
 6. The substrateof claim 1, further comprising: a) a barrier layer deposited on thesubstrate; b) a first dielectric layer deposited on the barrier layer;c) an etch stop deposited on the first dielectric layer; d) a seconddielectric layer deposited on the etch stop; wherein the silicon carbideanti-reflective coating is deposited on the second dielectric layer. 7.The substrate of claim 6, wherein a thickness of the anti-reflectivecoating is selected to result in a reflectivity of about 7 percent orless.
 8. The substrate of claim 7, wherein the thickness of theanti-reflective coating comprises a single selected thickness thatproduces a reflectivity of about 7 percent or less when the seconddielectric layer has a thickness from about 5000 Å to about 10000 Å. 9.The substrate of claim 8, wherein the barrier layer, etch stop, andanti-reflective coating comprises silicon carbide having a dielectricconstant less than 7.0.
 10. The substrate of claim 1, furthercomprising: a) a barrier layer deposited on the substrate; b) a firstdielectric layer deposited on the barrier layer; c) the silicon carbideanti-reflective coating deposited on the first dielectric layer; d) asecond dielectric layer deposited on the silicon carbide anti-reflectivecoating.
 11. The substrate of claim 10, further comprising selecting theanti-reflective coating having a thickness that produces a reflectivityof about 7 percent or less.
 12. A substrate having an anti-reflectivecoating, comprising: b) a barrier layer deposited on the substrate; c) afirst dielectric layer deposited on the barrier layer; d) an etch stopdeposited on the first dielectric layer; e) a second dielectric layerdeposited on the etch stop; f) an anti-reflective coating having asingle selected thickness that produces a reflectivity of about 7percent or less when the second dielectric layer has a thickness fromabout 5000 Å to about 10000 Å.
 13. The substrate of claim 12, whereinthe anti-reflective coating has a dielectric constant of less than 7.0.14. The substrate of claim 12, wherein the anti-reflective coatingcomprises silicon carbide.
 15. The substrate of claim 14, wherein thesilicon carbide is produced from an organosilane, independent ofseparate carbon or hydrogen sources from the organosilane.
 16. Thesubstrate of claim 14, wherein the anti-reflective coating comprisessilicon carbide that is produced by a process in a plasma reactor havinga chamber comprising providing an organosilane flow rate of betweenabout 30 to about 500 sccm as a silicon and carbon source and a noblegas flow rate of between about 100 to 2000 sccm and further comprisingreacting the silicon and the carbon in a chamber pressure range of about3 to about 10 Torr with an RF power source supplying a power density ofabout 4.3 to about 10.0 watts per square centimeter to an anode andcathode in the chamber and a substrate surface temperature of betweenabout 200° to about 400° C.
 17. The substrate of claim 12, wherein thesubstrate has an effective dielectric constant of 5 or less.
 18. Asubstrate having an anti-reflective coating, comprising: a) a firstdielectric layer deposited on the barrier layer; b) a silicon carbideanti-reflective coating deposited on the first dielectric layer; c) asecond dielectric layer deposited on the silicon carbide anti-reflectivecoating.
 19. The substrate of claim 18, wherein the silicon carbideanti-reflective coating has a dielectric constant of less than 7.0. 20.The substrate of claim 19, wherein the silicon carbide anti-reflectivecoating under the second dielectric layer produces a reflectivity ofabout 7 percent or less through the second dielectric layer.
 21. Thesubstrate of claim 18, wherein the silicon carbide anti-reflectivecoating is produced from an organosilane, independent of separate carbonsources from the organosilane.
 22. The substrate of claim 21, whereinthe silicon carbide is produced from an organosilane, independent ofseparate hydrogen sources from the organosilane.
 23. The substrate ofclaim 18, wherein the silicon carbide is produced by a process in aplasma reactor having a chamber comprising providing an organosilaneflow rate of between about 30 to about 500 sccm as a silicon and carbonsource and a noble gas flow rate of between about 100 to 2000 sccm andfurther comprising reacting the silicon and the carbon in a chamberpressure range of about 3 to about 10 Torr with an RF power sourcesupplying a power density of about 4.3 to about 10.0 watts per squarecentimeter to an anode and cathode in the chamber and a substratesurface temperature of between about 200° to about 400° C.
 24. A methodof forming a silicon carbide anti-reflective coating on a substrate,comprising: a) introducing silicon, carbon, and a noble gas into achamber; b) initiating a plasma in the chamber; b) reacting the siliconand the carbon in the presence of the plasma to form silicon carbide;and c) depositing a silicon carbide anti-reflection coating having a lowdielectric constant on the substrate in the chamber.
 25. The method ofclaim 24, wherein the silicon comprises a silane.
 26. The method ofclaim 24, wherein the silicon and carbon are derived from a commonorganosilane, independent of other carbon sources.
 27. The method ofclaim 24, wherein the silicon and carbon are derived from a commonsource, and reacting the silicon and the carbon in the presence of theplasma to form silicon carbide occurs independent of the presence of aseparate hydrogen source.
 28. The method of claim 24, wherein thesilicon and carbon are derived from a common source and reacting thesilicon and the carbon in the presence of the plasma to form siliconcarbide occurs independent of the presence of a separate carbon source.29. The method of claim 24, wherein the silicon carbide anti-reflectivecoating has an absorption index, a refraction index, and a coatingthickness and wherein the combination of the indexes and thicknessprovide an anti-reflective coating for the substrate having areflectivity of about 7 percent or less that is substantiallyindependent of a layer thickness of a dielectric layer adjacent theanti-reflective coating.
 30. The method of claim 29, wherein thesubstrate comprises a damascene structure.
 31. The method of claim 29,wherein the reflectivity of about 7 percent or less occurs when thedielectric layer thickness is about 5000 Å to about 10000 Å.
 32. Themethod of claim 24, wherein the low dielectric constant is less than7.0.
 33. The method of claim 24, further comprising selecting theanti-reflective coating that has a single selected thickness thatproduces a reflectivity of about 7 percent or less when an underlyingdielectric layer below the anti-reflective coating has a thickness fromabout 5000 Å to about 10000 Å.
 34. The method of claim 24, furthercomprising: a) depositing a barrier layer on the substrate; b)depositing a first dielectric layer on the barrier layer; c) depositingan etch stop on the first dielectric layer; d) depositing a seconddielectric layer on the etch stop; e) depositing the silicon carbideanti-reflective coating on the second dielectric layer.
 35. The methodof claim 34, further comprising selecting the anti-reflective coatingthat produces a reflectivity of about 7 percent or less.
 36. The methodof claim 35, further comprising selecting the anti-reflective coatingthat has a single selected thickness that produces a reflectivity ofabout 7 percent or less when the second dielectric layer has a thicknessfrom about 5000 Å to about 10000 Å.
 37. The method of claim 36, whereinthe second dielectric layer comprises a silicon glass material.
 38. Themethod of claim 34, wherein the barrier layer, etch stop, andanti-reflective coating comprises silicon carbide having a dielectricconstant less than 7.0.
 39. The method of claim 24, further comprising:b) depositing a barrier layer on the substrate; c) depositing a firstdielectric layer on the barrier layer; d) depositing the silicon carbideanti-reflective coating on the first dielectric layer; e) depositing asecond dielectric layer on the silicon carbide anti-reflective coating.40. The method of claim 39, further comprising selecting theanti-reflective coating with a reflectivity of about 7 percent or less.41. The method of claim 40, wherein the anti-reflective coating has adielectric constant of less than 7.0.
 42. The method of claim 24,further comprising depositing the silicon carbide anti-reflectivecoating at a temperature of between about 100° to about 450° C.
 43. Themethod of claim 24, further comprising depositing the silicon carbideanti-reflective coating at a temperature of between about 300° to about400° C.
 44. The method of claim 24, further comprising producing asubstrate having an effective dielectric constant of no greater thanabout
 5. 45. The method of claim 24, further comprising producing asilicon carbide anti-reflective coating that inhibits copper diffusionfrom a copper interface by about 3 orders of magnitude within about 300Å or less from the interface.
 46. The method of claim 24, whereinreacting the silicon and the carbon comprises reacting the silicon andthe carbon while maintaining a chamber pressure between about 6 to about10 Torr.
 47. The method of claim 24, wherein reacting the silicon andthe carbon comprises reacting the silicon and the carbon using an RFpower supply supplying a power density of about 4.3 to about 10.0 wattsper square centimeter to an anode and cathode in the chamber.
 48. Themethod of claim 24, wherein providing the silicon comprises providing asilane flow rate of between about 10 to about 1000 sccm and providingthe noble gas comprises providing a helium or argon flow rate of betweenabout 50 to about 5000 sccm.
 49. The method of claim 24, whereinproviding the silicon, the carbon, and the noble gas comprises providingan organosilane flow rate of between about 30 to about 500 sccm as thesilicon and carbon source and a helium or argon gas flow rate of betweenabout 100 to 2000 sccm as the noble gas source and further comprisingreacting the silicon and the carbon in a chamber pressure range of about3 to about 10 Torr with an RF power source supplying a power density ofabout 4.3 to about 10.0 watts per square centimeter to an anode andcathode in the chamber and a substrate surface temperature of betweenabout 200° to about 400° C.
 50. The substrate of claim 18, wherein athickness of the second dielectric layer is determined in conjunctionwith a thickness of the silicon carbide anti-reflective coating betweenthe first and second dielectric layer for a projected reflectivity. 51.The substrate of claim 18, wherein a thickness of the first dielectriclayer is determined in conjunction with a thickness of the siliconcarbide anti-reflective coating between the first and second dielectriclayer for a projected reflectivity.
 52. The method of claim 39, furthercomprising adjusting thicknesses of the first dielectric layer and thesilicon carbide anti-reflective coating between the first and seconddielectric layer for a projected reflectivity.
 53. The method of claim39, further comprising adjusting thicknesses of the second dielectriclayer and the silicon carbide anti-reflective coating between the firstand second dielectric layer for a projected reflectivity.
 54. The methodof claim 24, wherein the anti-reflective coating comprises a barrierlayer.
 55. A substrate having a silicon carbide anti-reflective coating,comprising: a) a dielectric layer deposited on the substrate; and b) thesilicon carbide anti-reflective coating having an absorption indexsubstantially related to the reflection index at a 248 nm exposurewavelength by the formula k/0.65+1.57=n, where k is the absorption indexand n is the reflection index.
 56. The substrate of claim 55, whereinthe k has a range of between about 0.3 to about 1.0.
 57. The substrateof claim 55, wherein the anti-reflective coating has a dielectricconstant of less than 7.0.
 58. The substrate of claim 55, wherein thesubstrate has an effective dielectric constant of about 5 or less. 59.The substrate of claim 55, wherein the silicon carbide anti-reflectivecoating is produced by the process of providing an organosilane flowrate of between about 30 to about 500 sccm as a silicon and carbonsource and a noble gas flow rate of between about 100 to 2000 sccm. 60.The method of claim 55, wherein the silicon carbide anti-reflectivecoating comprises a coating thickness and wherein the combination of theabsorption and reflection indexes and thickness provide ananti-reflective coating for the substrate having a reflectivity of about7 percent or less that is substantially independent of a layer thicknessof a dielectric layer adjacent the anti-reflective coating.
 61. Thesubstrate of claim 55, further comprising: a) a barrier layer depositedon the substrate; b) a first dielectric layer deposited on the barrierlayer; c) an etch stop deposited on the first dielectric layer; d) asecond dielectric layer deposited on the etch stop; wherein the siliconcarbide anti-reflective coating is deposited on the second dielectriclayer.
 62. The substrate of claim 55, further comprising: a) a barrierlayer deposited on the substrate; b) a first dielectric layer depositedon the barrier layer; c) the silicon carbide anti-reflective coatingdeposited on the first dielectric layer; d) a second dielectric layerdeposited on the silicon carbide anti-reflective coating.
 63. Thesubstrate of claim 55, further comprising: a) a barrier layer depositedon the substrate; b) a first dielectric layer deposited on the barrierlayer; wherein the silicon carbide anti-reflective coating comprises thebarrier layer.
 64. The substrate of claim 55, further comprising: a) abarrier layer deposited on the substrate; b) a first dielectric layerdeposited on the barrier layer wherein the silicon carbideanti-reflective coating is deposited on the first dielectric layer. 65.The method of claim 24, further comprising: a) depositing a barrierlayer comprising the anti-reflective coating, the barrier layer beingadjacent the substrate; b) depositing a first dielectric layer adjacentthe barrier layer; and c) depositing a photoresist layer adjacent thefirst dielectric layer.
 66. The method of claim 24, further comprising:a) depositing a barrier layer adjacent the substrate; b) depositing afirst dielectric layer adjacent the barrier layer; c) depositing theanti-reflective coating adjacent the first dielectric layer; and c)depositing a photoresist layer adjacent the anti-reflective coating.